A 2.1-μW 0.3V-1.0V wide locking range multiphase DLL using self-estimated SAR algorithm

Yi Ming Chang*, Ming Hung Chang, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper presents an all-digital multiphase delay-locked loop (ADMDLL) for wide-locking range and micro-power applications. To enhance locking range of the ADMDLL, we proposed the self-estimated successive approximation register-controlled (SESAR) algorithm, which uses the frequency-estimation selector (FES) to avoid harmonic lock issue. In addition, the FES can reuse the delay line to reduce circuit area and power dissipation significantly. By using the stack effect, the proposed leakage-reduced delay unit can save 12% leakage power consumption. After locking, the dynamic frequency monitor window is proposed to compensation phase error caused by PVT variations. The proposed ADMDLL is capable of operating in wide supply voltage range from 0.3V to 1.0V. The power dissipation is only 520μW at 1.25GHz/1.0V, and 2.1μW at 13MHz/0.3V, respectively. This work is based on UMC 90nm standard CMOS technology.

Original languageEnglish
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2009
Pages115-118
Number of pages4
DOIs
StatePublished - 1 Dec 2009
EventIEEE International SOC Conference, SOCC 2009 - Belfast, Ireland
Duration: 9 Sep 200911 Sep 2009

Publication series

NameProceedings - IEEE International SOC Conference, SOCC 2009

Conference

ConferenceIEEE International SOC Conference, SOCC 2009
CountryIreland
CityBelfast
Period9/09/0911/09/09

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