A single chip optical receiver comprising of a fontend amplifier, a CDR, and a 1:4 demultiplexer is presented. Incorporating with an integrating type receiver front-end, a baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operation. Besides, a hybrid loop filter consisting of analog decimation and digital post processing is proposed for high speed operation with low power consumption. By applying a PRBS 231-1 test pattern, the input sensitivity of the optical receiver is about -9.2 dBm for a BER of less than 10-12 (with a PD responsivity of 0.53 A/W). The recovered data jitter at the demultiplexer output is about 1.74 ps (rms). Implemented in a TSMC 40 nm CMOS process, the core area of the receiver chip is only 0.09 mm2. It demonstrates an energy efficiency of 2.4 pJ/bit for the entire receiver at 20 Gbps operation.