A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS

X. Shawn Wang*, Xin Jin, Jieqiong Du, Yilei Li, Yuan Du, Chien Heng Wong, Yen-Cheng Kuan, Chi Hang Chan, Mau-Chung Chang

*Corresponding author for this work

Research output: Contribution to journalArticle

3 Scopus citations

Abstract

This brief presents a two-way time-interleaved two-step pipelined analog-to-digital converter (ADC) architecture built upon a new concept of virtual-ground sampling, featuring merged front-end track-and-hold, residue generation, input termination, and buffering. This architecture is investigated to alleviate the front-end performance tradeoff among the total-harmonic-distortion, bandwidth, and sampling rate (interleaving factor). A 2-GS/s 8b ADC using the new architecture was designed and fabricated in 28-nm CMOS, achieving 43-dB SNDR and 55-dB SFDR up to Nyquist frequency.

Original languageEnglish
Article number8053825
Pages (from-to)1534-1538
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume65
Issue number11
DOIs
StatePublished - 1 Nov 2018

Keywords

  • Analog-to-digital converter (ADC)
  • SAR
  • time-interleaved
  • virtual-ground sampling

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