This brief presents a two-way time-interleaved two-step pipelined analog-to-digital converter (ADC) architecture built upon a new concept of virtual-ground sampling, featuring merged front-end track-and-hold, residue generation, input termination, and buffering. This architecture is investigated to alleviate the front-end performance tradeoff among the total-harmonic-distortion, bandwidth, and sampling rate (interleaving factor). A 2-GS/s 8b ADC using the new architecture was designed and fabricated in 28-nm CMOS, achieving 43-dB SNDR and 55-dB SFDR up to Nyquist frequency.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|State||Published - 1 Nov 2018|
- Analog-to-digital converter (ADC)
- virtual-ground sampling