TY - JOUR
T1 - A 2-GS/s 3-bit ΔΣ-modulated DAC with tunable bandpass mismatch shaping
AU - Kaplan, Todd S.
AU - Jensen, Joseph F.
AU - Fields, Charles H.
AU - Chang, Mau-Chung
PY - 2005/3/1
Y1 - 2005/3/1
N2 - Direct digital synthesis of signals in the hundreds of megahertz can lead to simpler, smaller transceivers, free of images and LO feedthrough that plague systems requiring analog upconversion. We present a 3-bit, 2 GS/s, ΔΣ-modulated DAC in InP HBT technology. The DAC is linearized using bandpass mismatch shaping. The mismatch shaper uses seven tunable 1.5-bit discrete-time bandpass ΔΣ modulators to dynamically route the digital signals to the DACs. These ΔΣ modulators operate in the analog domain to decrease system complexity and power consumption. The mismatch-shaped DAC can generate narrowband signals between 250-750 MHz with >68 dB SNR in a 1-MHz bw, >74-dB SFDR, and < -80-dBc intermodulation distortion with an 8.1-W power consumption.
AB - Direct digital synthesis of signals in the hundreds of megahertz can lead to simpler, smaller transceivers, free of images and LO feedthrough that plague systems requiring analog upconversion. We present a 3-bit, 2 GS/s, ΔΣ-modulated DAC in InP HBT technology. The DAC is linearized using bandpass mismatch shaping. The mismatch shaper uses seven tunable 1.5-bit discrete-time bandpass ΔΣ modulators to dynamically route the digital signals to the DACs. These ΔΣ modulators operate in the analog domain to decrease system complexity and power consumption. The mismatch-shaped DAC can generate narrowband signals between 250-750 MHz with >68 dB SNR in a 1-MHz bw, >74-dB SFDR, and < -80-dBc intermodulation distortion with an 8.1-W power consumption.
KW - Digital-analog conversion
KW - Dynamic element matching
KW - Mismatch shaping
KW - Sigma-delta modulation
UR - http://www.scopus.com/inward/record.url?scp=16244385650&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2005.843708
DO - 10.1109/JSSC.2005.843708
M3 - Article
AN - SCOPUS:16244385650
VL - 40
SP - 603
EP - 609
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 3
ER -