A 2-Gb/s/pin source synchronous CDMA bus interface with simultaneous multi-chip access and reconfigurable I/O capability

Jongsun Kim*, Zhiwei Xu, Mau-Chung Chang

*Corresponding author for this work

Research output: Contribution to journalConference article

10 Scopus citations

Abstract

A simultaneous reconfigurable multi-chip access bus interface for application in high-bandwidth multi-drop parallel interconnections such as memory bus has been developed. The interface utilizes source synchronous signaling + direct-sequence code-division multiple access (CDMA) technique for high bus concurrency and low channel latency. The prototype chip fabricated in 0.18-um CMOS and tested in a 10-cm test board achieves data rate of 2Gb/s/pin with multiple access and re-configurability between four (2-to-2) off-chip I/Os.

Original languageEnglish
Pages (from-to)317-320
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
DOIs
StatePublished - 19 Nov 2003
EventProceedings of the IEEE 2003 Custom Integrated Circuits Conference - San Jose, CA, United States
Duration: 21 Sep 200324 Sep 2003

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