A simultaneous reconfigurable multi-chip access bus interface for application in high-bandwidth multi-drop parallel interconnections such as memory bus has been developed. The interface utilizes source synchronous signaling + direct-sequence code-division multiple access (CDMA) technique for high bus concurrency and low channel latency. The prototype chip fabricated in 0.18-um CMOS and tested in a 10-cm test board achieves data rate of 2Gb/s/pin with multiple access and re-configurability between four (2-to-2) off-chip I/Os.
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - 19 Nov 2003|
|Event||Proceedings of the IEEE 2003 Custom Integrated Circuits Conference - San Jose, CA, United States|
Duration: 21 Sep 2003 → 24 Sep 2003