A 2-chip 1.5Gb/s bus-oriented serial link interface

Richard Walker, Jieh-Tsorng Wu, Cheryl Stout, Benny Lai, Chu Sun Yen, Tom Hornak, Pat Petruno

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

9 Scopus citations

Abstract

The authors report a monolithic transmitter and receiver chip pair which implements a full-duplex virtual ribbon cable interface. For short-distance applications, on-chip equalizer is provided to allow use of coaxial cables rather than a more costly fiber link. The chips require no external frequency-determining elements or user adjustments and operate over a range of 600 to 1500 MHz using an on-chip VCO (voltage-controlled oscillator). Only one in-package capacitor per chip is required. A state-machine controller (SMC) is also implemented on the RX chip to transparently handle a start-up handshake protocol. This is the highest-speed-link-interface chipset reported to date at this level of functionality and integration.

Original languageEnglish
Title of host publicationDigest Technical Papers - 1992 39th IEEE International Solid-State Circuits Conference, ISSCC 1992
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages226-227
Number of pages2
ISBN (Electronic)0780305736
DOIs
StatePublished - 1 Jan 1992
Event39th IEEE International Solid-State Circuits Conference, ISSCC 1992 - San Francisco, United States
Duration: 19 Feb 199221 Feb 1992

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume1992-February
ISSN (Print)0193-6530

Conference

Conference39th IEEE International Solid-State Circuits Conference, ISSCC 1992
CountryUnited States
CitySan Francisco
Period19/02/9221/02/92

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