A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS

Ming Hung Chang*, Yi Te Chiu, Shu Lin Lai, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

27 Scopus citations

Abstract

Subthreshold SRAM is a significant approach to reduce power consumption in energy-constrained SoC design. For the ultra-low power consideration, the primary concerns of SRAM are stability and reliability instead of performance. In this paper, the proposed 9T bit-cell enhances write ability by cutting off the positive feedback loop of inverter pair. In the read mode, the isolated read path and storage node enlarge the read SNM. Besides, a 9T subthreshold SRAM is proposed to enable implementation of bit-interleaving structure which achieves soft-error tolerance. The proposed SRAM is able to operate at a voltage as low as 0.3V. One extra virtual ground (VVSS) line is used to reduce the bit-line leakage to ensure the data can be read successfully. A 1kb bit-interleaved 9T SRAM is implemented in UMC 65nm 1P10M CMOS technology to verify the proposed scheme, which operates at the minimum energy point (0.3V) with 5.824pJ energy consumption for one write and one read operation.

Original languageEnglish
Title of host publicationIEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
Pages291-296
Number of pages6
DOIs
StatePublished - 19 Sep 2011
Event17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka, Japan
Duration: 1 Aug 20113 Aug 2011

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Conference

Conference17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
CountryJapan
CityFukuoka
Period1/08/113/08/11

Keywords

  • bit-interleaving scheme
  • subthreshold SRAM
  • ultra-low power

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