An ADPLL-based frequency synthesizer has been designed and implemented with TSMC 130nm technology model. The cores of it are digital controlled oscillator (DCO) and phase frequency detector (PFD). A modified digitally controlled delay element (DCDE) with characteristics of its monotonicity and insensitivity to PVT variations is presented for the DCO design. A new PFD architecture that can finish phase and frequency comparison and adjustment in one reference cycle is presented. This frequency synthesizer can operate from 300MHz to 1GHz, and achieve frequency acquisition in fifteen reference clock cycles (worst case scenario). The peak-to-peak jitter of the output clock is less than 120ps at 300MHz. Furthermore, the design has been ported to TSMC 100nm process as a reusable IP block verification. The total power dissipation of the ADPLL-based frequency synthesizer is 1.9mW (TSMC 100nm technology) at 1GHz with a 1.2V power supply. With such specifications, it is suitable for high speed clock generation in system-on-a-chip (SoC) applications.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 27 Sep 2007|
|Event||2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States|
Duration: 27 May 2007 → 30 May 2007