A 1.8 V, 10 Gbps fully integrated CMOS optical receiver analog front end

Wei-Zen Chen*, Ying Lien Cheng, Da Shin Lin

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

A fully integrated 10 Gbps optical receiver analog front-end, includes a trans-impedance amplifier (TIA) and a limiting amplifier (LA), is fabricated using a 0.18 μm CMOS technology. The receiver front-end provides a conversion gain up to 85 dB and -3 dB bandwidth of 7.6 GHz. The sensitivity of the optical receiver is -13 dBm at a bit-error rate of 10-12 with 231 - 1 pseudo-random bits. 3-D symmetric transformers are utilized in the AFE design for bandwidth enhancement.

Original languageEnglish
Title of host publicationESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference
EditorsM. Steyaert, C.L. Claeys
Pages263-266
Number of pages4
DOIs
StatePublished - 1 Dec 2004
EventESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference - Leuven, Belgium
Duration: 21 Sep 200423 Sep 2004

Publication series

NameESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference

Conference

ConferenceESSCIRC 2004 - Proceedings of the 30th European Solid-State Circuits Conference
CountryBelgium
CityLeuven
Period21/09/0423/09/04

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