@inproceedings{f62d9a784c1f418f9df14ed435e4abbd,
title = "A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits",
abstract = "This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18μm CMOS for low-power applications. The SAR ADC achieves a wide effective resolution bandwidth (ERBW) and a rail-to-rail signal swing by applying a limited number of bootstrapped switches. A robust low-voltage amplifier is proposed as the building block of the comparator. Measurement results show that at a supply voltage of 0.5-V and an output rate of 500S/s, the SAR ADC achieves a peak signal-to-noise-and- distortion ratio of 50.4 dB and an ERBW up to the Nyquist bandwidth (250 Hz). It consumes only 17 nW.",
author = "Kuo, {Rong Zhou} and Hao-Chiao Hong",
year = "2014",
month = jan,
day = "1",
doi = "10.1109/VLSI-DAT.2014.6834905",
language = "English",
isbn = "9781479927760",
series = "Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014",
publisher = "IEEE Computer Society",
booktitle = "Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014",
address = "United States",
note = "null ; Conference date: 28-04-2014 Through 30-04-2014",
}