A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits

Rong Zhou Kuo; Hao-Chiao Hong

doi:10.1109/VLSI-DAT.2014.6834905

A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits

Rong Zhou Kuo, Hao-Chiao Hong

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18μm CMOS for low-power applications. The SAR ADC achieves a wide effective resolution bandwidth (ERBW) and a rail-to-rail signal swing by applying a limited number of bootstrapped switches. A robust low-voltage amplifier is proposed as the building block of the comparator. Measurement results show that at a supply voltage of 0.5-V and an output rate of 500S/s, the SAR ADC achieves a peak signal-to-noise-and- distortion ratio of 50.4 dB and an ERBW up to the Nyquist bandwidth (250 Hz). It consumes only 17 nW.

Original language	English
Title of host publication	Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
Publisher	IEEE Computer Society
ISBN (Print)	9781479927760
DOIs	https://doi.org/10.1109/VLSI-DAT.2014.6834905
State	Published - 1 Jan 2014
Event	2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 - Hsinchu, Taiwan Duration: 28 Apr 2014 → 30 Apr 2014

Publication series

Name	Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

Conference

Conference	2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
Country	Taiwan
City	Hsinchu
Period	28/04/14 → 30/04/14

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10.1109/VLSI-DAT.2014.6834905

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Kuo, R. Z., & Hong, H-C. (2014). A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits. In Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 [6834905] (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014). IEEE Computer Society. https://doi.org/10.1109/VLSI-DAT.2014.6834905

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title = "A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits",

abstract = "This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18μm CMOS for low-power applications. The SAR ADC achieves a wide effective resolution bandwidth (ERBW) and a rail-to-rail signal swing by applying a limited number of bootstrapped switches. A robust low-voltage amplifier is proposed as the building block of the comparator. Measurement results show that at a supply voltage of 0.5-V and an output rate of 500S/s, the SAR ADC achieves a peak signal-to-noise-and- distortion ratio of 50.4 dB and an ERBW up to the Nyquist bandwidth (250 Hz). It consumes only 17 nW.",

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Kuo, RZ & Hong, H-C 2014, A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits. in Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014., 6834905, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014, IEEE Computer Society, 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014, Hsinchu, Taiwan, 28/04/14. https://doi.org/10.1109/VLSI-DAT.2014.6834905

A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits. / Kuo, Rong Zhou; Hong, Hao-Chiao.

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society, 2014. 6834905 (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18μm CMOS for low-power applications. The SAR ADC achieves a wide effective resolution bandwidth (ERBW) and a rail-to-rail signal swing by applying a limited number of bootstrapped switches. A robust low-voltage amplifier is proposed as the building block of the comparator. Measurement results show that at a supply voltage of 0.5-V and an output rate of 500S/s, the SAR ADC achieves a peak signal-to-noise-and- distortion ratio of 50.4 dB and an ERBW up to the Nyquist bandwidth (250 Hz). It consumes only 17 nW.

AB - This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18μm CMOS for low-power applications. The SAR ADC achieves a wide effective resolution bandwidth (ERBW) and a rail-to-rail signal swing by applying a limited number of bootstrapped switches. A robust low-voltage amplifier is proposed as the building block of the comparator. Measurement results show that at a supply voltage of 0.5-V and an output rate of 500S/s, the SAR ADC achieves a peak signal-to-noise-and- distortion ratio of 50.4 dB and an ERBW up to the Nyquist bandwidth (250 Hz). It consumes only 17 nW.

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Kuo RZ, Hong H-C. A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits. In Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society. 2014. 6834905. (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014). https://doi.org/10.1109/VLSI-DAT.2014.6834905

A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits

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