A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits

Rong Zhou Kuo, Hao-Chiao Hong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18μm CMOS for low-power applications. The SAR ADC achieves a wide effective resolution bandwidth (ERBW) and a rail-to-rail signal swing by applying a limited number of bootstrapped switches. A robust low-voltage amplifier is proposed as the building block of the comparator. Measurement results show that at a supply voltage of 0.5-V and an output rate of 500S/s, the SAR ADC achieves a peak signal-to-noise-and- distortion ratio of 50.4 dB and an ERBW up to the Nyquist bandwidth (250 Hz). It consumes only 17 nW.

Original languageEnglish
Title of host publicationTechnical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
PublisherIEEE Computer Society
ISBN (Print)9781479927760
DOIs
StatePublished - 1 Jan 2014
Event2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 - Hsinchu, Taiwan
Duration: 28 Apr 201430 Apr 2014

Publication series

NameTechnical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

Conference

Conference2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
CountryTaiwan
CityHsinchu
Period28/04/1430/04/14

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    Kuo, R. Z., & Hong, H-C. (2014). A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits. In Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 [6834905] (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014). IEEE Computer Society. https://doi.org/10.1109/VLSI-DAT.2014.6834905