A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS

Ming Zhang Kuo; Henry Hsieh; Sang Dhong; Ping Lin Yang; Cheng Chung Lin; Ryan Tseng; Kevin Huang; Min Jer Wang; Wei Hwang

doi:10.1109/CICC.2014.6946030

A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS

Ming Zhang Kuo, Henry Hsieh, Sang Dhong, Ping Lin Yang, Cheng Chung Lin, Ryan Tseng, Kevin Huang, Min Jer Wang, Wei Hwang

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

This paper describes a tile-able 16-kByte 6-T SRAM macro in a High-K Metal-Gate (HKMG) 28-nm bulk technology with an operating window from 4.8 GHz at 1.12 V VDD down to 10 MHz at 0.5V, meeting almost all of the Dynamic Voltage Frequency Scaling (DVFS) requirements of Level-1 (L1) caches of a digital microprocessor SOC. It uses an unmodified technology-supported 0.156um² high-current (HC) SRAM cell. Innovative and carefully optimized circuit solutions provide the wide operating range measured in hardware. We also discuss two circuit improvements, a cross-coupled PMOS-pair for each bitline-pair with mux readout and an independently-controlled precharge-and-write driver (ICPW), which gives a wider DVFS operating window with reduced sensitivities to Process-Voltageerature (PVT) variations. Improved SRAM macros with new circuits have been designed and laid out and their performance and area verified in simulation.

Original language	English
Title of host publication	Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479932863
DOIs	https://doi.org/10.1109/CICC.2014.6946030
State	Published - 4 Nov 2014
Event	36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014 - San Jose, United States Duration: 15 Sep 2014 → 17 Sep 2014

Publication series

Name	Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014

Conference

Conference	36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014
Country	United States
City	San Jose
Period	15/09/14 → 17/09/14

Keywords

Cross-coupled PMOS-pair
DVFS
independently controlled precharge-and-write driver (ICPW)
SRAM

Access to Document

10.1109/CICC.2014.6946030

Fingerprint Dive into the research topics of 'A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS'. Together they form a unique fingerprint.

Cite this

Kuo, M. Z., Hsieh, H., Dhong, S., Yang, P. L., Lin, C. C., Tseng, R., Huang, K., Wang, M. J., & Hwang, W. (2014). A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014 [6946030] (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2014.6946030

Kuo, Ming Zhang ; Hsieh, Henry ; Dhong, Sang ; Yang, Ping Lin ; Lin, Cheng Chung ; Tseng, Ryan ; Huang, Kevin ; Wang, Min Jer ; Hwang, Wei. / A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc., 2014. (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014).

@inproceedings{517716a97476465dae0e604bb33eb838,

title = "A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS",

abstract = "This paper describes a tile-able 16-kByte 6-T SRAM macro in a High-K Metal-Gate (HKMG) 28-nm bulk technology with an operating window from 4.8 GHz at 1.12 V VDD down to 10 MHz at 0.5V, meeting almost all of the Dynamic Voltage Frequency Scaling (DVFS) requirements of Level-1 (L1) caches of a digital microprocessor SOC. It uses an unmodified technology-supported 0.156um2 high-current (HC) SRAM cell. Innovative and carefully optimized circuit solutions provide the wide operating range measured in hardware. We also discuss two circuit improvements, a cross-coupled PMOS-pair for each bitline-pair with mux readout and an independently-controlled precharge-and-write driver (ICPW), which gives a wider DVFS operating window with reduced sensitivities to Process-Voltageerature (PVT) variations. Improved SRAM macros with new circuits have been designed and laid out and their performance and area verified in simulation.",

keywords = "Cross-coupled PMOS-pair, DVFS, independently controlled precharge-and-write driver (ICPW), SRAM",

author = "Kuo, {Ming Zhang} and Henry Hsieh and Sang Dhong and Yang, {Ping Lin} and Lin, {Cheng Chung} and Ryan Tseng and Kevin Huang and Wang, {Min Jer} and Wei Hwang",

year = "2014",

month = nov,

day = "4",

doi = "10.1109/CICC.2014.6946030",

language = "English",

series = "Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014",

address = "United States",

note = "null ; Conference date: 15-09-2014 Through 17-09-2014",

}

Kuo, MZ, Hsieh, H, Dhong, S, Yang, PL, Lin, CC, Tseng, R, Huang, K, Wang, MJ & Hwang, W 2014, A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. in Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014., 6946030, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, Institute of Electrical and Electronics Engineers Inc., 36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014, San Jose, United States, 15/09/14. https://doi.org/10.1109/CICC.2014.6946030

A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. / Kuo, Ming Zhang; Hsieh, Henry; Dhong, Sang; Yang, Ping Lin; Lin, Cheng Chung; Tseng, Ryan; Huang, Kevin; Wang, Min Jer; Hwang, Wei.

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 6946030 (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS

AU - Kuo, Ming Zhang

AU - Hsieh, Henry

AU - Dhong, Sang

AU - Yang, Ping Lin

AU - Lin, Cheng Chung

AU - Tseng, Ryan

AU - Huang, Kevin

AU - Wang, Min Jer

AU - Hwang, Wei

PY - 2014/11/4

Y1 - 2014/11/4

N2 - This paper describes a tile-able 16-kByte 6-T SRAM macro in a High-K Metal-Gate (HKMG) 28-nm bulk technology with an operating window from 4.8 GHz at 1.12 V VDD down to 10 MHz at 0.5V, meeting almost all of the Dynamic Voltage Frequency Scaling (DVFS) requirements of Level-1 (L1) caches of a digital microprocessor SOC. It uses an unmodified technology-supported 0.156um2 high-current (HC) SRAM cell. Innovative and carefully optimized circuit solutions provide the wide operating range measured in hardware. We also discuss two circuit improvements, a cross-coupled PMOS-pair for each bitline-pair with mux readout and an independently-controlled precharge-and-write driver (ICPW), which gives a wider DVFS operating window with reduced sensitivities to Process-Voltageerature (PVT) variations. Improved SRAM macros with new circuits have been designed and laid out and their performance and area verified in simulation.

AB - This paper describes a tile-able 16-kByte 6-T SRAM macro in a High-K Metal-Gate (HKMG) 28-nm bulk technology with an operating window from 4.8 GHz at 1.12 V VDD down to 10 MHz at 0.5V, meeting almost all of the Dynamic Voltage Frequency Scaling (DVFS) requirements of Level-1 (L1) caches of a digital microprocessor SOC. It uses an unmodified technology-supported 0.156um2 high-current (HC) SRAM cell. Innovative and carefully optimized circuit solutions provide the wide operating range measured in hardware. We also discuss two circuit improvements, a cross-coupled PMOS-pair for each bitline-pair with mux readout and an independently-controlled precharge-and-write driver (ICPW), which gives a wider DVFS operating window with reduced sensitivities to Process-Voltageerature (PVT) variations. Improved SRAM macros with new circuits have been designed and laid out and their performance and area verified in simulation.

KW - Cross-coupled PMOS-pair

KW - DVFS

KW - independently controlled precharge-and-write driver (ICPW)

KW - SRAM

UR - http://www.scopus.com/inward/record.url?scp=84928157681&partnerID=8YFLogxK

U2 - 10.1109/CICC.2014.6946030

DO - 10.1109/CICC.2014.6946030

M3 - Conference contribution

AN - SCOPUS:84928157681

T3 - Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014

BT - Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 15 September 2014 through 17 September 2014

ER -

Kuo MZ, Hsieh H, Dhong S, Yang PL, Lin CC, Tseng R et al. A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 6946030. (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014). https://doi.org/10.1109/CICC.2014.6946030