@inproceedings{517716a97476465dae0e604bb33eb838,
title = "A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS",
abstract = "This paper describes a tile-able 16-kByte 6-T SRAM macro in a High-K Metal-Gate (HKMG) 28-nm bulk technology with an operating window from 4.8 GHz at 1.12 V VDD down to 10 MHz at 0.5V, meeting almost all of the Dynamic Voltage Frequency Scaling (DVFS) requirements of Level-1 (L1) caches of a digital microprocessor SOC. It uses an unmodified technology-supported 0.156um2 high-current (HC) SRAM cell. Innovative and carefully optimized circuit solutions provide the wide operating range measured in hardware. We also discuss two circuit improvements, a cross-coupled PMOS-pair for each bitline-pair with mux readout and an independently-controlled precharge-and-write driver (ICPW), which gives a wider DVFS operating window with reduced sensitivities to Process-Voltageerature (PVT) variations. Improved SRAM macros with new circuits have been designed and laid out and their performance and area verified in simulation.",
keywords = "Cross-coupled PMOS-pair, DVFS, independently controlled precharge-and-write driver (ICPW), SRAM",
author = "Kuo, {Ming Zhang} and Henry Hsieh and Sang Dhong and Yang, {Ping Lin} and Lin, {Cheng Chung} and Ryan Tseng and Kevin Huang and Wang, {Min Jer} and Wei Hwang",
year = "2014",
month = nov,
day = "4",
doi = "10.1109/CICC.2014.6946030",
language = "English",
series = "Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014",
address = "United States",
note = "null ; Conference date: 15-09-2014 Through 17-09-2014",
}