A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS

Ming Zhang Kuo, Henry Hsieh, Sang Dhong, Ping Lin Yang, Cheng Chung Lin, Ryan Tseng, Kevin Huang, Min Jer Wang, Wei Hwang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

This paper describes a tile-able 16-kByte 6-T SRAM macro in a High-K Metal-Gate (HKMG) 28-nm bulk technology with an operating window from 4.8 GHz at 1.12 V VDD down to 10 MHz at 0.5V, meeting almost all of the Dynamic Voltage Frequency Scaling (DVFS) requirements of Level-1 (L1) caches of a digital microprocessor SOC. It uses an unmodified technology-supported 0.156um2 high-current (HC) SRAM cell. Innovative and carefully optimized circuit solutions provide the wide operating range measured in hardware. We also discuss two circuit improvements, a cross-coupled PMOS-pair for each bitline-pair with mux readout and an independently-controlled precharge-and-write driver (ICPW), which gives a wider DVFS operating window with reduced sensitivities to Process-Voltageerature (PVT) variations. Improved SRAM macros with new circuits have been designed and laid out and their performance and area verified in simulation.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479932863
DOIs
StatePublished - 4 Nov 2014
Event36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014 - San Jose, United States
Duration: 15 Sep 201417 Sep 2014

Publication series

NameProceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014

Conference

Conference36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014
CountryUnited States
CitySan Jose
Period15/09/1417/09/14

Keywords

  • Cross-coupled PMOS-pair
  • DVFS
  • independently controlled precharge-and-write driver (ICPW)
  • SRAM

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