A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit

Po Chun Liu*, Hsie-Chia Chang, Chen-Yi Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

14 Scopus citations

Abstract

The AES algorithm published in 2001 is now the most popular symmetric encryption algorithm. Several implementations have beed proposed but few of them considered the hardware cost and the throughput as a whole. This paper presents an AES core to be capable of both encryption and decryption with three different key lengths: 128-, 192-, and 256-bit. The overall hardware cost was optimized by a very compact on-the-fly key expansion unit and a highly integrated encryption/decryption datapath. The compact on-the-fly key expansion unit is achieved by sharing expansion processes of different key lengths. The integrated data datapath shares hardware resources between encryption and decryption. After manufactured in 90nm CMOS technology, the area of the chip is 15,577 equivalent gates with throughput up to 1.69 Gb/s operating at 131.8 MHz.

Original languageEnglish
Title of host publicationESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference
Pages404-407
Number of pages4
DOIs
StatePublished - 1 Dec 2009
Event35th European Solid-State Circuits Conference, ESSCIRC 2009 - Athens, Greece
Duration: 14 Sep 200918 Sep 2009

Publication series

NameESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference

Conference

Conference35th European Solid-State Circuits Conference, ESSCIRC 2009
CountryGreece
CityAthens
Period14/09/0918/09/09

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