A 160kGate 4.5kB SRAM H.264 video decoder for HDTV applications

C. C. Lin*, Jiun-In  Guo, H. C. Chang, Y. C. Yang, J. W. Chen, M. C. Tsai, J. S. Wang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

22 Scopus citations

Abstract

Through both algorithmic and architectural optimization, the H.264 video decoder dissipates 320mW at 1.8V when operating at 120MHz for HD1080 (1920×1088 at 30frames/s). The die contains 160kgates 4.5kB memory and occupies 2.9×2.9mm2 in 0.18μm CMOS.

Original languageEnglish
Title of host publication2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
DOIs
StatePublished - 1 Dec 2006
Event2006 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States
Duration: 6 Feb 20069 Feb 2006

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Conference

Conference2006 IEEE International Solid-State Circuits Conference, ISSCC
CountryUnited States
CitySan Francisco, CA
Period6/02/069/02/06

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