In this paper, a low-cost H.264/AVC video decoder design is presented for high definition television (HDTV) applications. Through optimization from algorithmic and architectural perspectives, the proposed design can achieve real-time H.264 video decoding on HD1080 video (1920 × 1088@30 Hz) when operating at 120 MHz with 320 m W power dissipation. Fabricated by using the TSMC one-poly six-metal 0.18 μm CMOS technology, the proposed design occupies 2.9 × 2.9 mm 2 silicon area with the hardware complexity of 160K gates and 4.5K bytes of local memory.
- H264/AVC video decoder architecture design
- Low power consumption
- Low-cost design