A 160K gates/4.5 KB SRAM H.264 video decoder for HDTV applications

Chien Chang Lin*, Jia Wei Chen, Hsiu Cheng Chang, Yao Chang Yang, Yi Huan Ou Yang, Ming Chih Tsai, Jiun-In  Guo, Jinn Shyan Wang

*Corresponding author for this work

Research output: Contribution to journalArticle

52 Scopus citations


In this paper, a low-cost H.264/AVC video decoder design is presented for high definition television (HDTV) applications. Through optimization from algorithmic and architectural perspectives, the proposed design can achieve real-time H.264 video decoding on HD1080 video (1920 × 1088@30 Hz) when operating at 120 MHz with 320 m W power dissipation. Fabricated by using the TSMC one-poly six-metal 0.18 μm CMOS technology, the proposed design occupies 2.9 × 2.9 mm 2 silicon area with the hardware complexity of 160K gates and 4.5K bytes of local memory.

Original languageEnglish
Pages (from-to)170-181
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Issue number1
StatePublished - 1 Jan 2007


  • H264/AVC video decoder architecture design
  • Low power consumption
  • Low-cost design

Fingerprint Dive into the research topics of 'A 160K gates/4.5 KB SRAM H.264 video decoder for HDTV applications'. Together they form a unique fingerprint.

  • Cite this

    Lin, C. C., Chen, J. W., Chang, H. C., Yang, Y. C., Yang, Y. H. O., Tsai, M. C., Guo, J-I., & Wang, J. S. (2007). A 160K gates/4.5 KB SRAM H.264 video decoder for HDTV applications. IEEE Journal of Solid-State Circuits, 42(1), 170-181. https://doi.org/10.1109/JSSC.2006.886537