A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology

Wei-Zen Chen*, Tai You Lu, Yan Ting Wang, Jhong Ting Jian, Yi Hung Yang, Guo Wei Huang, Wen De Liu, Chih Hua Hsiao, Shu Yu Lin, Jung Yen Liao

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

A 160-GHz receiver-based PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3 rd harmonic mixer incorporating frequency tripler for frequency down conversion. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatically frequency sweeping and fast locking. The frequency locking time is less than 3 μsec. Fabricated in 65 nm CMOS technology, the chip size is 0.92mm 2. This chip drains 24mW from a 1.2V power supply.

Original languageEnglish
Title of host publication2012 Symposium on VLSI Circuits, VLSIC 2012
Pages12-13
Number of pages2
DOIs
StatePublished - 28 Sep 2012
Event2012 Symposium on VLSI Circuits, VLSIC 2012 - Honolulu, HI, United States
Duration: 13 Jun 201215 Jun 2012

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference2012 Symposium on VLSI Circuits, VLSIC 2012
CountryUnited States
CityHonolulu, HI
Period13/06/1215/06/12

Keywords

  • Mixer
  • PLL
  • RSSI
  • THz

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