A 160-GHz frequency-translation phase-locked loop with RSSI assisted frequency acquisition

Wei-Zen Chen, Tai You Lu, Yan Ting Wang, Jhong Ting Jian, Yi Hung Yang, Kai Ting Chang

Research output: Contribution to journalArticle

6 Scopus citations

Abstract

A 160-GHz frequency-translation PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3rd harmonic mixer incorporating a frequency tripler for frequency down conversion. A transformer-based VCO is utilized to alleviate capacitive and resistive load associated with varactor and succeeding buffer stages. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatic frequency sweeping and fast locking. Fabricated in 65 nm CMOS technology, the chip size is 0.92 mm2. The PLL locking time is less than 3 μ s. This chip drains 24 mW from a 1.2 V power supply.

Original languageEnglish
Article number6728756
Pages (from-to)1648-1655
Number of pages8
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume61
Issue number6
DOIs
StatePublished - 1 Jan 2014

Keywords

  • Harmonic mixer
  • PLL
  • RSSI
  • tripler

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