A 16-mW 8-bit 1-GS/s subranging ADC in 55nm CMOS

Yung Hui Chung*, Jieh-Tsorng Wu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Scopus citations

Abstract

An 8-bit subranging ADC was fabricated using a 55nm CMOS technology. To enhance speed, subranging is executed by activating comparators in the digital domain. To save power, comparators are latches with automatic offset calibration. Operating at 1GHz sampling rate, the ADC consumes 16mW from a 1.2V supply. The measured DNL is 0.8LSB and INL is 1.2LSB. The measured SFDR and SNDR are 55dB and 43.5dB respectively. The ADC occupies an active area of 0.2mm 2. Its FOM is 125fJ/conversion-step.

Original languageEnglish
Title of host publication2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers
Pages128-129
Number of pages2
StatePublished - 16 Sep 2011
Event2011 Symposium on VLSI Circuits, VLSIC 2011 - Kyoto, Japan
Duration: 15 Jun 201117 Jun 2011

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference2011 Symposium on VLSI Circuits, VLSIC 2011
CountryJapan
CityKyoto
Period15/06/1117/06/11

Keywords

  • Analog-digital conversion
  • calibration
  • comparators (circuits)
  • subranging ADC

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    Chung, Y. H., & Wu, J-T. (2011). A 16-mW 8-bit 1-GS/s subranging ADC in 55nm CMOS. In 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers (pp. 128-129). [5986070] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).