A 16-mW 8-Bit 1-GS/s digital-subranging ADC in 55-nm CMOS

Yung Hui Chung, Jieh-Tsorng Wu

Research output: Contribution to journalArticle

12 Scopus citations

Abstract

This paper presents a digital-subranging (sub-R) analog-to-digital conversion (ADC) architecture to improve the operation speed of sub-R ADCs. Long latency between coarse and fine conversions will slow down the conventional sub-R ADCs. The proposed digital-sub-R uses digital circuits to implement the sub-R function and shorten this latency, thus benefits the CMOS scaling. Furthermore, the dynamic comparators are used to save more ADC power consumption. Their accuracy is improved by the proposed pseudodifferential offset calibration loop. The digital-sub-R also helps to reduce the dynamic offset of the fine comparators caused by the input common-mode variation. Fabricated using a 55-nm CMOS technology, the reported 8-bit 1-GS/s ADC consumes only 16 mW from a 1.2 V supply. Measured signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR) are 46 and 55 dB, respectively. Measured effective number of bits (ENOB) is seven bits at 10-MHz input frequency. At Nyquist input, the ENOB performance of 6.3 bits is still maintained. Its figure-of-merit is 197-fJ/conversion-step.

Original languageEnglish
Article number6782419
Pages (from-to)557-566
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume23
Issue number3
DOIs
StatePublished - 1 Mar 2015

Keywords

  • Analog-to-digital conversion (ADC)
  • CMOS
  • comparator (circuits)
  • offset calibration
  • subranging (sub-R) ADC.

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