A 15b 20MS/s CMOS pipelined ADC with digital background calibration

Hung Chih Liu*, Zwei Mei Lee, Jieh-Tsorng Wu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

31 Scopus citations

Abstract

A 15b 20MS/s CMOS pipelined ADC is fabricated in a 0.18μm dual-gate CMOS technology and achieves 94dB SFDR and 74dB SNDR for a 8MHz input. Digital calibration can proceed continuously in the background to maintain the ADC resolution. The chip occupies an area of 3.3 × 3.4mm 2 and dissipates 235mW with 1.8V and 3.3V dual supplies.

Original languageEnglish
Pages (from-to)374-375+625
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume47
DOIs
StatePublished - 2 Jun 2004
EventDigest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference - San Francisco, CA., United States
Duration: 15 Feb 200319 Feb 2003

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