A 15b 20MS/s CMOS pipelined ADC is fabricated in a 0.18μm dual-gate CMOS technology and achieves 94dB SFDR and 74dB SNDR for a 8MHz input. Digital calibration can proceed continuously in the background to maintain the ADC resolution. The chip occupies an area of 3.3 × 3.4mm 2 and dissipates 235mW with 1.8V and 3.3V dual supplies.
|Journal||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|State||Published - 2 Jun 2004|
|Event||Digest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference - San Francisco, CA., United States|
Duration: 15 Feb 2003 → 19 Feb 2003