A 1.5 mW Programmable Acoustic Signal Processor for Hearing Assistive Devices With Speech Intelligibility Enhancement

Yung-Jen Lin, Yu-Chi Lee, Hao-Min Liu, Herming Chiueh, Tai-Shih Chi, Chia-Hsiang Yang*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


This paper presents a low-power, programmable acoustic signal processor for hearing assistive devices with speech intelligibility enhancement. The reprogrammable design provides considerable flexibility for the devices to deal with personal conditions of hearing loss. A spectral-change enhancement (SCE) algorithm is implemented to improve speech intelligibility. The power consumption is minimized by adding dedicated hardware accelerators. The short-time objective intelligibility (STOI) measure is utilized for optimizing the datapath architecture. Optimization on the critical MAC operations results in 34% power and area reductions when compared to the direct-mapped design. A 50% reduction in SRAM storage is also achieved owing to the reduced memory storage for the associated MAC operations. With the aid of the optimized MAC unit and data buffer, the overall execution time is reduced by 99.2%. Designed in a 40-nm CMOS technology, the processor integrates 431k gates in area of 0.3 mm(2). The design dissipates 1.5 mW at a clock frequency of 10.5 MHz from a 0.7V supply, with a processing latency of 1.05 ms.

Original languageEnglish
Pages (from-to)4984-4993
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number12
StatePublished - Dec 2020


  • Signal processing algorithms
  • Auditory system
  • Acoustics
  • Speech enhancement
  • Dogs
  • Ear
  • Assistive devices
  • Hearing assitive device
  • digital signal processing (DSP)
  • speech intelligibility enhancement
  • CMOS integrated circuits
  • low-power VLSI

Cite this