A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration

Hung Chih Liu*, Zwei Mei Lee, Jieh-Tsorng Wu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

76 Scopus citations

Abstract

This study presents a 15-b 40-MS/s switched-capacitor CMOS pipelined analog-to-digital converter (ADC). High resolution is achieved by using a correlation-based background calibration technique that can continuously monitor the transfer characteristics of the critical pipeline stages and correct the digital output codes accordingly. The calibration can correct errors associated with capacitor mismatches and finite opamp gains. The ADC was fabricated using a 0.25-μm 1P5M CMOS technology. Operating at a 40-MS/s sampling rate, the ADC attains a maximum signal-to-noise-plus-distortion ratio of 73.5 dB and a maximum spurious-free-dynamic-range of 93.3 dB. The chip occupies an area of 3.8 × 3.6 mm2, and the power consumption is 370 mW with a single 2.5-V supply.

Original languageEnglish
Pages (from-to)1047-1055
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume40
Issue number5
DOIs
StatePublished - 1 May 2005

Keywords

  • Analog-digital conversion
  • Calibration
  • Mixed analog-digital integrated circuits

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