A 1.45Gb/s (576,288) LDPC decoder for 802.16e standard

Jui Hui Hung*, Sau-Gee Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

In this work, a (576,288) LDPC decoder for 802.16e standard is presented. This design is a partially parallel architecture based on a new optimally reordered decoding scheme. Besides, the proposed architecture handles two different code words at a time to achieve 100% utilization rate of both CNU and BNU. As a result, high throughput and low hardware complexity are achieved. In chip implementation, the proposed design achieves a data rate of 1.45Gb/s with 10 iterations and 7 quantization bits, at the cost of 881K gates, based on UMC 0.187mu;m process technology.

Original languageEnglish
Title of host publicationISSPIT 2007 - 2007 IEEE International Symposium on Signal Processing and Information Technology
Pages916-921
Number of pages6
DOIs
StatePublished - 1 Dec 2007
EventISSPIT 2007 - 2007 IEEE International Symposium on Signal Processing and Information Technology - Cairo, Egypt
Duration: 15 Dec 200718 Dec 2007

Publication series

NameISSPIT 2007 - 2007 IEEE International Symposium on Signal Processing and Information Technology

Conference

ConferenceISSPIT 2007 - 2007 IEEE International Symposium on Signal Processing and Information Technology
CountryEgypt
CityCairo
Period15/12/0718/12/07

Keywords

  • Architecture
  • Decoder
  • LDPC code

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    Hung, J. H., & Chen, S-G. (2007). A 1.45Gb/s (576,288) LDPC decoder for 802.16e standard. In ISSPIT 2007 - 2007 IEEE International Symposium on Signal Processing and Information Technology (pp. 916-921). [4458033] (ISSPIT 2007 - 2007 IEEE International Symposium on Signal Processing and Information Technology). https://doi.org/10.1109/ISSPIT.2007.4458033