A 135mW fully integrated data processor for next-generation sequencing

Yi Chung Wu, Jui-Hung Hung, Chia Hsiang Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

DNA sequencing is the process of determining the precise order of nucleotides (A, C, G, T) within a DNA molecule and is now indispensable for genetics and medical research. Next-generation sequencing (NGS), in which short DNA fragments can be sequenced in a massively parallel fashion, enables high-throughput sequencing [1]. However, the succeeding data analysis, also known as DNA mapping, is excessively time consuming. DNA mapping can be partitioned into Suffix Array (SA) Sorting and Backward Searching. Dedicated hardware designs have been proposed to enhance the speed, but only for the less complex Backward Searching [2]. Feasible hardware for the most complicated part, SA sorting, has never been explored. This work presents a fully integrated NGS data processor that realizes both SA sorting and Backward Searching. The distributed sort algorithm is utilized to reduce the sorting complexity. The throughput of SA sorting is maximized through 2,048 insertion-sorting elements. Dedicated overflow and splitter caches are embedded to reduce the computation latency. With the optimized hardware architecture, the NGS processor achieves orders of magnitude improvement in both energy and throughput metrics compared to the high-end generic processors.

Original languageEnglish
Title of host publication2017 IEEE International Solid-State Circuits Conference, ISSCC 2017
EditorsLaura C. Fujino
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages252-253
Number of pages2
ISBN (Electronic)9781509037575
DOIs
StatePublished - 2 Mar 2017
Event64th IEEE International Solid-State Circuits Conference, ISSCC 2017 - San Francisco, United States
Duration: 5 Feb 20179 Feb 2017

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume60
ISSN (Print)0193-6530

Conference

Conference64th IEEE International Solid-State Circuits Conference, ISSCC 2017
CountryUnited States
CitySan Francisco
Period5/02/179/02/17

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  • Cite this

    Wu, Y. C., Hung, J-H., & Yang, C. H. (2017). A 135mW fully integrated data processor for next-generation sequencing. In L. C. Fujino (Ed.), 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017 (pp. 252-253). [7870356] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 60). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2017.7870356