A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications

Xin Ru Lee*, Chih Wen Yang, Chih Lung Chen, Hsie-Chia Chang, Chen-Yi Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this paper, an over Gb/s stochastic nonbinary LDPC (NB-LDPC) decoder chip is first-reported. The operation of proposed decoder is transformed to logarithm domain, so that the decoding complexity is mitigated by the simpler summations and fewer bit-width. In addition, the storage requirements are dramatically reduced by truncated TFM architecture. After, benefited from architecture optimizations and symbol-serial property, the routing capability of proposed decoder is extraordinarily enhanced. According to the measurement results, this decoder can deliver 1.31Gb/s throughput under 368MHz clock frequency with the corresponding energy-efficiency of 0.45nJ/bit. Compared to other NB-LDPC decoders, our stochastic NB-LDPC decoder with 96.6% chip utilization improves 2x area-efficiency and 7x energy-efficiency.

Original languageEnglish
Title of host publicationESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference
EditorsFranz Dielacher, Wolfgang Pribyl, Gernot Hueber
PublisherIEEE Computer Society
Pages96-99
Number of pages4
ISBN (Electronic)9781467374705
DOIs
StatePublished - 30 Oct 2015
Event41st European Solid-State Circuits Conference, ESSCIRC 2015 - Graz, Austria
Duration: 14 Sep 201518 Sep 2015

Publication series

NameEuropean Solid-State Circuits Conference
Volume2015-October
ISSN (Print)1930-8833

Conference

Conference41st European Solid-State Circuits Conference, ESSCIRC 2015
CountryAustria
CityGraz
Period14/09/1518/09/15

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