A 1.2V interference-sturdiness, dc-offset calibrated cmos receiver utilizing a current-mode filter for uwb

Horng Yuan Shih, Wei Hsien Chen, Kai Chenug Juang, Tzu Yi Yang, Chien-Nan Kuo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

An interference-sturdiness receiver with a current-mode filter for 3-5GHz UWB applications is implemented in a 1.2V 0.13(im CMOS process. The chip provides a maximum voltage gain of 70dB and a dynamic range of 60dB. The measured in-band OIP3 is +9.39dBm, out-of-band IIP3 -15dBm and noise figure 6.8dB in the maximum gain mode. An algorithm for the automatic digital DC offset calibration is also demonstrated.

Original languageEnglish
Title of host publicationProceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Pages345-348
Number of pages4
DOIs
StatePublished - 1 Dec 2008
Event2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan
Duration: 3 Nov 20085 Nov 2008

Publication series

NameProceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Conference

Conference2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
CountryJapan
CityFukuoka
Period3/11/085/11/08

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