A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz

Wei Hsin Tseng*, Chi Wei Fan, Jieh-Tsorng Wu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Scopus citations

Abstract

The current-steering DACs are commonly used in generating high-frequency signals [1-4]. A current-steering DAC comprises current cells of various sizes. Each of them contains a current source and a current switch. The DAC static linearity, specified as differential nonlinearity (DNL) and integral nonlinearity (INL), is mainly determined by the mutual matching and the output resistance of the current sources. The DAC also exhibits dynamic distortion. It is manifested as spurious-free dynamic range (SFDR) degradation. The SFDR decreases rapidly with increasing input frequency. There are two major sources of dynamic distortion, code-dependent switching transients (CDST) and code-dependent output-loading variation (CDLV). Switching transients are temporal disturbances in DAC output when the current switches in current cells make transitions. The output loading of a DAC varies when the output impedances of current cells change due to the transposition of their current switches. This DAC applies a digital random return-to-zero (DRRZ) technique to mitigate the CDST effect. Compact current cells are designed to minimize the CDLV effect. The current mismatches of the current cells are corrected by background calibration.

Original languageEnglish
Title of host publication2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011
Pages192-193
Number of pages2
DOIs
StatePublished - 12 May 2011
Event2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, CA, United States
Duration: 20 Feb 201124 Feb 2011

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Conference

Conference2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
CountryUnited States
CitySan Francisco, CA
Period20/02/1124/02/11

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    Tseng, W. H., Fan, C. W., & Wu, J-T. (2011). A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz. In 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011 (pp. 192-193). [5746278] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2011.5746278