A digital-to-phase converter (DPC) generates a 125MHz clock with phase shift controlled by an 8b digital input. Averaging resistor rings are used for phase interpolation and phase error reduction by averaging. Implemented in a standard 0.35μm CMOS technology, the DPC achieves ±1LSB differential nonlinearity and ±2LSB integral nonlinearity. Power dissipation is 110mW with a 3.3V supply.
|Journal||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|State||Published - 23 Jul 2003|
|Event||2003 Digest of Technical Papers - , United States|
Duration: 9 Feb 2003 → 13 Feb 2003