A 125MHz 8b digital-to-phase converter

Ju Ming Chou*, Yu Tang Hsieh, Jieh-Tsorng Wu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

12 Scopus citations

Abstract

A digital-to-phase converter (DPC) generates a 125MHz clock with phase shift controlled by an 8b digital input. Averaging resistor rings are used for phase interpolation and phase error reduction by averaging. Implemented in a standard 0.35μm CMOS technology, the DPC achieves ±1LSB differential nonlinearity and ±2LSB integral nonlinearity. Power dissipation is 110mW with a 3.3V supply.

Original languageEnglish
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
DOIs
StatePublished - 23 Jul 2003
Event2003 Digest of Technical Papers - , United States
Duration: 9 Feb 200313 Feb 2003

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