A 125 mm2 1 Gb NAND flash uses 0.13 μm CMOS. The cell is 0.077 μm2. Chip architecture is changed to reduce chip size and to realize 10.6 MB/s throughput for program and 20 MB/s for read. An on-chip page copy function provides 9.4 MB/s throughput for garbage collection.
|Journal||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|State||Published - 1 Jan 2002|
|Event||2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States|
Duration: 3 Feb 2002 → 7 Feb 2002