A 125 mm2 1 Gb NAND flash memory with 10 Mb/s program throughput

Hiroshi Nakamura*, Kenichi Imamiya, Toshihiko Himeno, Toshio Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Koichi Kawai, Shirota Riichiro, Norihisa Arai, Fumitaka Arai, Kazuo Hatakeyama, Hiroaki Hazama, Masanobu Saito, Hisataka Meguro, Kevin Conley, Khandker Quader, Jian Chen

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

3 Scopus citations

Abstract

A 125 mm2 1 Gb NAND flash uses 0.13 μm CMOS. The cell is 0.077 μm2. Chip architecture is changed to reduce chip size and to realize 10.6 MB/s throughput for program and 20 MB/s for read. An on-chip page copy function provides 9.4 MB/s throughput for garbage collection.

Original languageEnglish
Pages (from-to)82-83+411
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Issue numberSUPPL.
DOIs
StatePublished - 1 Jan 2002
Event2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States
Duration: 3 Feb 20027 Feb 2002

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