A 125 mm 2 1 Gb NAND flash memory with 10 MB/s program throughput was presented. The 1 Gb flash has the highest memory density among 2LC memories and the highest cell/chip efficiency among flash memories. Two techniques were adopted in the architecture for reducing the chip size, the number of memory cells in a NAND string was changed to 32 and each word line (WL) crossed (1024+32)×16 bit lines.
|Journal||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|State||Published - 1 Jan 2002|
|Event||2002 IEEE International Solid-State Circuits Conference - San Francisco, CA, United States|
Duration: 3 Feb 2002 → 7 Feb 2002