A 12.5 gbps CMOS input sampler for serial link receiver front end

Shyh-Jye Jou*, Chih Hsien Lin, Yen I. Wang

*Corresponding author for this work

Research output: Contribution to journalConference article

Abstract

This paper presents a high-speed CMOS input sampler used for serial link receiver front end. The input sampler consists of a comparator, a SR latch and a D flip-flop. Because a parallel architecture is used for the 1:8 demultiplexing and 3x oversampliing is utilized for data recovery, there are 24 input samplers in receiver front end. These input samplers are implemented in TSMC0.18um 1P6M process with area of 252*162 um 2 . The circuits can operate at maximum input data rate of 12.7 Gbps with differential signal of 300 mV using supply voltage of 1.8V.

Original languageEnglish
Article number1464773
Pages (from-to)1055-1058
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
DOIs
StatePublished - 1 Dec 2005
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: 23 May 200526 May 2005

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