A 125 μW, fully scalable MPEG-2 and H.264/AVC video decoder for mobile applications

Tsu Ming Liu*, Ting An Lin, Sheng Zen Wang, Wen Ping Lee, Jiun Yan Yang, Kang Cheng Hou, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

45 Scopus citations


A low-power dual-standard video decoder has been developed for mobile applications. It supports MPEG-2 SP@ML and H.264/AVC BL@L4 video decoding in a single chip and features a scalable architecture to reach area/power efficiency. This chip integrates diverse algorithms of MPEG-2 and H.264/AVC to reduce silicon area. Three low-power techniques are proposed. First, a domain-pipelined scalability (DPS) technique is used to optimize the pipelined structure according to the number of processing cycles. Second, bandwidth scalability is implemented via a line-pixel-lookahead (LPL) scheme to improve the external bandwidth and reduce the internal memory size, leading to 51% of memory power reduction compared to a conventional design. Third, low-power motion compensation and deblocking filter are designed to reduce the operating frequency without degrading system performance. A test chip is fabricated in a 0.18 μm one-poly six-metal CMOS technology with an area of 15.21 mm 2. For mobile applications, H.264/AVC and MPEG-2 video decoding of quarter-common intermediate format (QCIF) sequences at 15 frames per second are achieved at 1.15 MHz clock frequency with power dissipation of 125 μW and 108 μW, respectively, at 1 V supply voltage.

Original languageEnglish
Pages (from-to)161-169
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Issue number1
StatePublished - 1 Jan 2007


  • H.264/AVC
  • Inverse discrete cosine transform (IDCT)
  • MPEG-2
  • Mobile communication
  • Motion compensation
  • Video coding

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