A 12-bit 1.25-GS/s DAC in 90 nm CMOS with > 70 dB SFDR up to 500 MHz

Wei Hsin Tseng*, Chi Wei Fan, Jieh-Tsorng Wu

*Corresponding author for this work

Research output: Contribution to journalArticle

51 Scopus citations

Abstract

A current-steering digital-to-analog converter (DAC) was fabricated using a 90 nm CMOS technology. Its dynamic performance is enhanced by adopting a digital random return-to-zero (DRRZ) operation and a compact current cell design. The DRRZ also facilitates a current-cell background calibration technique that ensures the DAC static linearity. The measured differential nonlinearity (DNL) is 0.5 LSB and the integral nonlinearity (INL) is 1.2 LSB. At 1.25 GS/s sampling rate, the DAC achieves a spurious-free dynamic range (SFDR) better than 70 dB up to 500 MHz input frequency. The DAC occupies an active area of 1100 × 750 μm2. It consumes a total of 128 mW from a 1.2 V and a 2.5 V supply.

Original languageEnglish
Article number6021346
Pages (from-to)2845-2856
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Volume46
Issue number12
DOIs
StatePublished - 1 Dec 2011

Keywords

  • Background calibration
  • current-steering
  • D/A converters
  • digital random return-to-zero (DRRZ)
  • digital-analog conversion
  • digital-to-analog converter (DAC)
  • return-to-zero (RZ)

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