A 11.5-Gbps LDPC decoder based on CP-PEG code construction

Chih Lung Chen*, Kao Shou Lin, Hsie-Chia Chang, Wai-Chi Fang, Chen-Yi Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Scopus citations

Abstract

In this paper, a LDPC decoder chip based on CP-PEG code construction is presented. The (2048, 1920) irregular LDPC code generated by CP-PEG algorithm has better performance than other PEG-based codes; however, the large check node degrees introduced by high code-rate 15/16 become the implementation bottleneck. To design such a high code-rate LDPC decoder, our approach features variable-node-centric sequential scheduling to reduce iteration number, single piplelined decoder architecture to lessen the message storage memory size, as well as optimized check node unit to further compress the register number. Overall 73% message storage memory is saved as compared with traditional architecture. Fabricated in 90nm 1P9M CMOS technology, a test deocder chip could achieve maximum 11.5 Gbps throughput under 1.4V supply voltage with core area of 2.7 × 1.4 mm2. The energy efficiency is only 0.033 nJ/bit with 5.77 Gbps at 0.8V to meet IEEE 802.15.3c requirements.

Original languageEnglish
Title of host publicationESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference
Pages412-415
Number of pages4
DOIs
StatePublished - 1 Dec 2009
Event35th European Solid-State Circuits Conference, ESSCIRC 2009 - Athens, Greece
Duration: 14 Sep 200918 Sep 2009

Publication series

NameESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference

Conference

Conference35th European Solid-State Circuits Conference, ESSCIRC 2009
CountryGreece
CityAthens
Period14/09/0918/09/09

Keywords

  • High throughput
  • LDPC
  • Sequential scheduling

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    Chen, C. L., Lin, K. S., Chang, H-C., Fang, W-C., & Lee, C-Y. (2009). A 11.5-Gbps LDPC decoder based on CP-PEG code construction. In ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference (pp. 412-415). [5325933] (ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2009.5325933