A 11μW 250 Hz BW two-step incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor interfaces

Chia-Hung Chen, Yi Zhang, Tao He, Patrick Y. Chiang, Gabor C. Temes

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

16 Scopus citations

Abstract

A two-step incremental ADC (IADC) is proposed for low-bandwidth, micro-power sensor interface circuits. This architecture extends the order of a conventional IADC from N to (2N-1) by using a two-step operation, while requiring only the circuitry of an Nth-order IADC. The implemented third-order IADC achieves a measured dynamic range of 99.8 dB and an SNDR of 91 dB for a maximum input 2.2 VPP and 250 Hz bandwidth. Fabricated in 65 nm CMOS, the IADC's core area is 0.2 mm2, and consumes only 10.7 μW. The FoMs are 0.76 pJ/conversion-step and 173.5 dB, both among the best reported results.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479932863
DOIs
StatePublished - 4 Nov 2014
Event36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014 - San Jose, United States
Duration: 15 Sep 201417 Sep 2014

Publication series

NameProceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014

Conference

Conference36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014
CountryUnited States
CitySan Jose
Period15/09/1417/09/14

Keywords

  • Analog-to-digital Converter (ADC)
  • chopper stabilization
  • decimation filter
  • delta sigma (ΔΣ)
  • extended-counting
  • incremental data converter
  • micro-power
  • oversampling
  • sensor interface

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