A 10Gb/s 44.2 dB adaptive equalizer with Duobinary tracking loop in 0.18μm CMOS

Po Hsuan Chang, An Siou Li, Chia-Ming Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents an adaptive equalizer that converts the attenuated signal into Duobinary signaling scheme, combined with automatic Duobinary tracking technique to produce high quality Duobinary signal for simplifying the Duobinary decoding process and achieving higher data rate. The adaptive equalizer uses dual gain-mode topology that allows higher gain when the received signal is highly attenuated, and allows lower power consumption when the received signals pass through low-attenuation channel. A background offset cancellation loop circuit is added to increase the clock phase margin of the equalizer. The chip is fabricated in 0.18μm CMOS technology and operates at data rate of 10 Gb/s. The measurement results show that the equalizer recovers data properly for FR-4 trace with length ranging from 3 inches to 66 inches. The equalizer achieves clock phase margin of 58 % for 66-inch channel with BER less than 10-12 and consumes power of 28.4 mW under high gain mode with 1.8V power supply.

Original languageEnglish
Title of host publication2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2133-2136
Number of pages4
ISBN (Print)9781479934324
DOIs
StatePublished - 1 Jan 2014
Event2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
Duration: 1 Jun 20145 Jun 2014

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
CountryAustralia
CityMelbourne, VIC
Period1/06/145/06/14

Keywords

  • Adaptive
  • Decision Feedback Equalizer
  • Duobinary
  • Equalizer
  • offset cancellation

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