A 1.08-Gb/s burst-mode clock and data recovery circuit using the jitter reduction technique

Kae D. You*, Her-Ming Chiueh

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

A 1.08-Gb/s CMOS half-rate burst-mode clock and data recovery (BMCDR) circuit with a novel jitter reduction technique is presented. There are several discrete delay time values in the programmable delay circuit (PDC) of the edge detector can be selected by five addressing inputs to create a "dynamic average" delay time that equals to half-of-data period (Tbit/2) to ensure minimum jitter accumulation. A prototype chip was designed with TSMC 0.18-μm CMOS 1P6M technology. The occupied die area of the CDR is 0.99 x 0.97 mm 2, and the power consumption is 36 mW under a 1.8-V supply voltage.

Original languageEnglish
Title of host publication2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Pages1899-1902
Number of pages4
DOIs
StatePublished - 26 Oct 2009
Event2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan
Duration: 24 May 200927 May 2009

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
CountryTaiwan
CityTaipei
Period24/05/0927/05/09

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    You, K. D., & Chiueh, H-M. (2009). A 1.08-Gb/s burst-mode clock and data recovery circuit using the jitter reduction technique. In 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 (pp. 1899-1902). [5118151] (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2009.5118151