A 100-MHz Pipelined CMOS Comparator

Jieh-Tsorng Wu, Bruce A. Wooley

Research output: Contribution to journalArticlepeer-review

58 Scopus citations

Abstract

This paper describes the design of a VLSI-compatible CMOS comparator for high-speed applications. An examination of various generic approaches to obtaining the nonlinear “amplification” needed to perform the function of comparison leads to the conclusion that this amplification can best be obtained by means of regeneration. Based on this conclusion, a CMOS comparator has been designed wherein voltage comparisons are accomplished directly by means of a pipelined cascade of two regenerative sense amplifiers, without the use of a preamplifier. To ensure an input resolution of at least 8 bits, offset cancellation is incorporated in the first sense amplifier. In addition, an input sampling network comprised of only passive devices is used to sample the two analog inputs and cancel their common-mode voltage. The comparator has been integrated in a 2-üm CMOS technology and has a maximum sampling rate of over 100 MHz; it operates from a single +5-V supply and dissipates only 3.6 mW at its maximum sampling rate.

Original languageEnglish
Pages (from-to)1379-1385
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Volume23
Issue number6
DOIs
StatePublished - 1 Jan 1988

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