For the first time, 10nm Si-based bulk FinFETs 6T SRAM (beta ratio = 2) with novel multiple fin heights technology is successfully demonstrated with 25% better static noise margin at 0.6 V than single fin-height baseline. Meanwhile, presented technology also provides advantage in SRAM cell size by 20% scaling down. It can furthermore offer potential of beyond 10nm Si-based CMOS computing circuit technology.
|Title of host publication||2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers|
|State||Published - 17 Sep 2013|
|Event||2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan|
Duration: 12 Jun 2013 → 14 Jun 2013
|Name||IEEE Symposium on VLSI Circuits, Digest of Technical Papers|
|Conference||2013 Symposium on VLSI Circuits, VLSIC 2013|
|Period||12/06/13 → 14/06/13|