A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin

Min Cheng Chen, Chang Hsien Lin, Yun Fang Hou, Yi Ju Chen, Chia Yi Lin, Fu Kuo Hsueh, Hsin Liang Liu, Cheng Tsai Liu, Bo Wei Wang, Hsiu Chih Chen, Chun Chi Chen, Shih Hung Chen, Chien Ting Wu, Tung Yen Lai, Mei Yi Lee, Bo Wei Wu, Cheng San Wu, Ivy Yang, Yi Ping Hsieh, Chiahua HoTa-Hui Wang, Angada B. Sachid, Chen-Ming Hu, Fu Liang Yang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

9 Scopus citations

Abstract

For the first time, 10nm Si-based bulk FinFETs 6T SRAM (beta ratio = 2) with novel multiple fin heights technology is successfully demonstrated with 25% better static noise margin at 0.6 V than single fin-height baseline. Meanwhile, presented technology also provides advantage in SRAM cell size by 20% scaling down. It can furthermore offer potential of beyond 10nm Si-based CMOS computing circuit technology.

Original languageEnglish
Title of host publication2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
StatePublished - 17 Sep 2013
Event2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan
Duration: 12 Jun 201314 Jun 2013

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference2013 Symposium on VLSI Circuits, VLSIC 2013
CountryJapan
CityKyoto
Period12/06/1314/06/13

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