A 10-Gb/s low jitter single-loop clock and data recovery circuit with rotational phase frequency detector

Fan Ta Chen*, Min Sheng Kao, Yu Hao Hsu, Jen Ming Wu, Ching Te Chiu, Shawn S.H. Hsu, Mau-Chung Chang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

11 Scopus citations

Abstract

This paper presents a rotational phase frequency detector (RPFD) for reference-less clock and data recovery circuit (CDR). The proposed RPFD changes the bang-bang phase detector (BBPD) characteristic from a bidirectional phase detection to an unilateral phase detection for capturing clock frequency. The phase-and-frequency lock loop (PFLL) locks the clock frequency and the clock phase alternatively. The single-loop CDR replaces the dual-loop CDR so as to eliminate the noise contribution from the frequency lock loop (FLL). This proposed design is fabricated in TSMC mixed-signal 1P9M 90-nm standard CMOS process with overall die size of 0.71-{\rm mm}2. With input 10-Gb/s data of a 2{31}-1 PRBS, the CDR tracks free running clock over the capture range of 1.48 GHz and locks in the acquisition time of 20 \mu{\rm s}. At the same time, the peak-to-peak jitters show only 5.0 ps in the recovered clock and exhibits 15.11 ps in the recovered data. The measured chip consumes 92 mW with 1.0-V supply voltage.

Original languageEnglish
Article number6856236
Pages (from-to)3278-3287
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume61
Issue number11
DOIs
StatePublished - 1 Nov 2014

Keywords

  • Bang-bang phase detector (BBPD)
  • clock and data recovery (CDR)
  • frequency detector (FD)

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