A 10-bit DAC with 1.6-bit interpolation cells for compact LCD column driver ics

Chih Wen Lu*, Ching Min Hsiao, Yo Sheng Lin, Mau-Chung Chang

*Corresponding author for this work

Research output: Contribution to journalArticle

11 Scopus citations

Abstract

This paper proposes a 10-bit DAC for LCD column driver ICs. This architecture achieves 10-bit resolution with a compact die size smaller than that of a conventional 8-bit resistor-string DAC (RDAC). The proposed DAC combines a 6-bit RDAC and a 4-bit DAC-embedded op with 1.6-bit current-mode interpolation cells. The 6-bit RDAC uses a one-voltage selector instead of a two-voltage selector; therefore, it requires a smaller silicon die area for the voltage selector. Fewer differential pairs are required for the voltage interpolation because the DAC-embedded op uses 1.6-bit interpolation cells with binary-weighted reference voltages. This further reduces the silicon die area. The 10-bit DAC prototype was realized in 0.35-μm CMOS technology with the worst DNL/INL of 0.45/0.93 LSB. The 10-bit DAC occupies only 64% of the conventional 8-bit RDAC area.

Original languageEnglish
Article number6459556
Pages (from-to)176-183
Number of pages8
JournalIEEE/OSA Journal of Display Technology
Volume9
Issue number3
DOIs
StatePublished - 20 Feb 2013

Keywords

  • Column driver
  • DAC
  • DAC-embedded op
  • LCD

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