A 10-Bit 200-MS/s digitally-calibrated pipelined ADC using switching opamps

Bing Nan Fang; Jieh-Tsorng Wu

doi:10.1109/ISCAS.2012.6271406

A 10-Bit 200-MS/s digitally-calibrated pipelined ADC using switching opamps

Bing Nan Fang^*, Jieh-Tsorng Wu

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Contribution to conference › Paper › peer-review

2 Scopus citations

Abstract

A 10-bit 200-MS/s pipelined ADC was fabricated using a 90 nm CMOS technology. Switching opamps are used to save power. They are designed for high speed and fast turn-on time. Digital background calibration is used to correct the conversion error caused by the low dc gain of the opamps. The ADC consumes 26 mW from a 1.1 V supply. Its measured DNL and INL are +0.98/0.81 LSB and +1.4/1.5 LSB respectively. Its measured SNDR and SFDR are 55 dB and 67.2 dB respectively. The chip active area is 0.69 mm ².

Original language	English
Pages	1042-1045
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271406
State	Published - 28 Sep 2012
Event	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: 20 May 2012 → 23 May 2012

Conference

Conference	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country	Korea, Republic of
City	Seoul
Period	20/05/12 → 23/05/12

Access to Document

10.1109/ISCAS.2012.6271406

Fingerprint Dive into the research topics of 'A 10-Bit 200-MS/s digitally-calibrated pipelined ADC using switching opamps'. Together they form a unique fingerprint.

Cite this

@conference{501351f334ce430aab67219804700943,

title = "A 10-Bit 200-MS/s digitally-calibrated pipelined ADC using switching opamps",

abstract = "A 10-bit 200-MS/s pipelined ADC was fabricated using a 90 nm CMOS technology. Switching opamps are used to save power. They are designed for high speed and fast turn-on time. Digital background calibration is used to correct the conversion error caused by the low dc gain of the opamps. The ADC consumes 26 mW from a 1.1 V supply. Its measured DNL and INL are +0.98/0.81 LSB and +1.4/1.5 LSB respectively. Its measured SNDR and SFDR are 55 dB and 67.2 dB respectively. The chip active area is 0.69 mm 2.",

author = "Fang, {Bing Nan} and Jieh-Tsorng Wu",

year = "2012",

month = sep,

day = "28",

doi = "10.1109/ISCAS.2012.6271406",

language = "English",

pages = "1042--1045",

note = "null ; Conference date: 20-05-2012 Through 23-05-2012",

}

TY - CONF

T1 - A 10-Bit 200-MS/s digitally-calibrated pipelined ADC using switching opamps

AU - Fang, Bing Nan

AU - Wu, Jieh-Tsorng

PY - 2012/9/28

Y1 - 2012/9/28

N2 - A 10-bit 200-MS/s pipelined ADC was fabricated using a 90 nm CMOS technology. Switching opamps are used to save power. They are designed for high speed and fast turn-on time. Digital background calibration is used to correct the conversion error caused by the low dc gain of the opamps. The ADC consumes 26 mW from a 1.1 V supply. Its measured DNL and INL are +0.98/0.81 LSB and +1.4/1.5 LSB respectively. Its measured SNDR and SFDR are 55 dB and 67.2 dB respectively. The chip active area is 0.69 mm 2.

AB - A 10-bit 200-MS/s pipelined ADC was fabricated using a 90 nm CMOS technology. Switching opamps are used to save power. They are designed for high speed and fast turn-on time. Digital background calibration is used to correct the conversion error caused by the low dc gain of the opamps. The ADC consumes 26 mW from a 1.1 V supply. Its measured DNL and INL are +0.98/0.81 LSB and +1.4/1.5 LSB respectively. Its measured SNDR and SFDR are 55 dB and 67.2 dB respectively. The chip active area is 0.69 mm 2.

UR - http://www.scopus.com/inward/record.url?scp=84866606168&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2012.6271406

DO - 10.1109/ISCAS.2012.6271406

M3 - Paper

AN - SCOPUS:84866606168

SP - 1042

EP - 1045

Y2 - 20 May 2012 through 23 May 2012

ER -

A 10-Bit 200-MS/s digitally-calibrated pipelined ADC using switching opamps

Abstract

Conference

Access to Document

Other files and links

Cite this