A 10-Bit 200-MS/s digitally-calibrated pipelined ADC using switching opamps

Bing Nan Fang*, Jieh-Tsorng Wu

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

2 Scopus citations

Abstract

A 10-bit 200-MS/s pipelined ADC was fabricated using a 90 nm CMOS technology. Switching opamps are used to save power. They are designed for high speed and fast turn-on time. Digital background calibration is used to correct the conversion error caused by the low dc gain of the opamps. The ADC consumes 26 mW from a 1.1 V supply. Its measured DNL and INL are +0.98/0.81 LSB and +1.4/1.5 LSB respectively. Its measured SNDR and SFDR are 55 dB and 67.2 dB respectively. The chip active area is 0.69 mm 2.

Original languageEnglish
Pages1042-1045
Number of pages4
DOIs
StatePublished - 28 Sep 2012
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: 20 May 201223 May 2012

Conference

Conference2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
CountryKorea, Republic of
CitySeoul
Period20/05/1223/05/12

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