@inproceedings{c59568391117499c86775c782f35f065,
title = "A 10-bit 10 MS/s SAR ADC with the reduced capacitance DAC",
abstract = "This paper presents a 10-bit 10 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 180 nm technology. We propose a new structure of the charge redistribution digital-to-analog converter (DAC) for the SAR ADC to reduce the area cost and power consumption and to promote the bandwidth. This structure does not only reduce the area of capacitors array and the capacitance of the DAC, but also guarantee the process variation of capacitors.",
keywords = "analog-to-digital converter (ADC), capacitor, charge redistribution, digital-to-analog converter (DAC), successive approximation register (SAR)",
author = "Kuo, {Hsuan Lun} and Lu, {Chih Wen} and Lin, {Shuw Guann} and Chang, {Da Chiang}",
year = "2016",
month = aug,
day = "12",
doi = "10.1109/ISNE.2016.7543361",
language = "English",
series = "2016 5th International Symposium on Next-Generation Electronics, ISNE 2016",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2016 5th International Symposium on Next-Generation Electronics, ISNE 2016",
address = "United States",
note = "null ; Conference date: 04-05-2016 Through 06-05-2016",
}