A 10-bit 10 MS/s SAR ADC with the reduced capacitance DAC

Hsuan Lun Kuo, Chih Wen Lu, Shuw Guann Lin, Da Chiang Chang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

This paper presents a 10-bit 10 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 180 nm technology. We propose a new structure of the charge redistribution digital-to-analog converter (DAC) for the SAR ADC to reduce the area cost and power consumption and to promote the bandwidth. This structure does not only reduce the area of capacitors array and the capacitance of the DAC, but also guarantee the process variation of capacitors.

Original languageEnglish
Title of host publication2016 5th International Symposium on Next-Generation Electronics, ISNE 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509024391
DOIs
StatePublished - 12 Aug 2016
Event5th International Symposium on Next-Generation Electronics, ISNE 2016 - Hsinchu, Taiwan
Duration: 4 May 20166 May 2016

Publication series

Name2016 5th International Symposium on Next-Generation Electronics, ISNE 2016

Conference

Conference5th International Symposium on Next-Generation Electronics, ISNE 2016
CountryTaiwan
CityHsinchu
Period4/05/166/05/16

Keywords

  • analog-to-digital converter (ADC)
  • capacitor
  • charge redistribution
  • digital-to-analog converter (DAC)
  • successive approximation register (SAR)

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