A 1-V RF-CMOS LNA design utilizing the technique of capacitive feedback matching network

Fadi Riad Shahroury, Chung-Yu Wu*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

In this paper, a CMOS low-noise amplifier (LNA) with a new input matching topology has been proposed, analyzed and measured. The input matching network is designed through the technique of capacitive feedback matching network. The proposed LNA which is implemented in a 0.18 - μ m 1 P 6 M CMOS technology is operated at the frequency of 12.8 GHz. It has a gain S21 of 13.2 dB, a noise figure (NF) of 4.57 dB and an NFmin of 4.46 dB. The reverse isolation S12 of the LNA can achieve - 40 dB and the input and output return losses are better than - 11 dB. The input 1-dB compression point is - 11 dB m and IIP3 is - 0.5 dB m. This LNA drains 10 mA from the supply voltage of 1 V.

Original languageEnglish
Pages (from-to)83-88
Number of pages6
JournalIntegration, the VLSI Journal
Volume42
Issue number1
DOIs
StatePublished - 1 Jan 2009

Keywords

  • Low voltage
  • Low-noise amplifier (LNA)
  • Noise optimization
  • RF

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