A 1-V input, 0.2-V to 0.47-V output switched-capacitor DC-DC converter with Pulse Density and Width Modulation (PDWM) for 57% ripple reduction

Xin Zhang*, Yu Pu, Koichi Ishida, Yoshikatsu Ryu, Yasuyuki Okuma, Po-Hung Chen, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

9 Scopus citations

Abstract

To effectively reduce output ripple of switched-capacitor DC-DC converters which generate variable output voltages, a novel feedback control scheme is presented. The proposed scheme uses pulse density and width modulation (PDWM) to reduce the output ripple with low output voltage. The prototype chip was implemented using 65nm CMOS process. The switched-capacitor DC-DC converter has 0.2-V to 0.47-V output voltage and delivers 0.25-mA to 10-mA output current from a 1-V input supply with a peak efficiency of 87%. Compared with the conventional pulse density modulation (PDM), the proposed switched-capacitor DC-DC converter with PDWM reduces the output ripple by 57% in the low output voltage region with the efficiency penalty of 2%.

Original languageEnglish
Title of host publication2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
Pages61-64
Number of pages4
DOIs
StatePublished - 1 Dec 2010
Event2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010 - Beijing, China
Duration: 8 Nov 201010 Nov 2010

Publication series

Name2010 IEEE Asian Solid-State Circuits Conference, A-SSCC 2010

Conference

Conference2010 6th IEEE Asian Solid-State Circuits Conference, A-SSCC 2010
CountryChina
CityBeijing
Period8/11/1010/11/10

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