A 1 v 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback

Yi Zhang, Chia Hung Chen, Tao He, Xin Meng, Nancy Qian, Ed Liu, Phillip Elliott, Gabor C. Temes

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

A 3rd-order continuous-time ΔΣ modulator with a highly-digital excess loop delay compensation and multi-bit FIR feedback, to be used in an ultrasound beamformer, is presented. A digitally controlled reference switching matrix avoids the power-hungry adder, and allows a power-efficient design of the loop filter. A 2-bit 3-tap FIR feedback DAC optimally achieves lower sensitivity to clock jitter and applies reduced error signal to the loop filter, thus enhancing the loop filter linearity. The modulator operates at 1.2 GHz, and achieves 79.4 dB dynamic range, 77.3 dB SNR and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies 0.16 mm2 and dissipates 6.96mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit is achieved.

Original languageEnglish
Title of host publication2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages321-324
Number of pages4
ISBN (Electronic)9781479940905
DOIs
StatePublished - 13 Jan 2015
Event2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 - Kaohsiung, Taiwan
Duration: 10 Nov 201412 Nov 2014

Publication series

Name2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers

Conference

Conference2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014
CountryTaiwan
CityKaohsiung
Period10/11/1412/11/14

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