A 1 v 175 μw 94.6 dB SNDR 25 kHz bandwidth delta-sigma modulator using segmented integration techniques

Sheng Hui Liao, Jieh-Tsorng Wu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

A 2-1 MASH switched-capacitor delta-sigma modulator was fabricated using a 65 nm CMOS technology. We constantly alternate the circuit configurations of its internal integrators to optimize power consumption. The integrators are accelerated only when they are in crucial integration cycle. Operating at 5 MS/s sampling rate, this chip consumes 175 μW from a 1 V supply. Assuming a 25 kHz signal bandwidth, it achieves 96.1 dB SNR, 94.6 dB SNDR, and 98.5 dB DR. Its active area is 113 × 0 34 mm2.

Original languageEnglish
Title of host publication2018 IEEE Custom Integrated Circuits Conference, CICC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-4
Number of pages4
ISBN (Electronic)9781538624838
DOIs
StatePublished - 9 May 2018
Event2018 IEEE Custom Integrated Circuits Conference, CICC 2018 - San Diego, United States
Duration: 8 Apr 201811 Apr 2018

Publication series

Name2018 IEEE Custom Integrated Circuits Conference, CICC 2018

Conference

Conference2018 IEEE Custom Integrated Circuits Conference, CICC 2018
CountryUnited States
CitySan Diego
Period8/04/1811/04/18

Keywords

  • Delta-sigma modulator
  • MASH
  • analog-digital conversion
  • switched-capacitor circuit

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