A 1-V 175-μ W 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques

Sheng Hui Liao, Jieh-Tsorng Wu

Research output: Contribution to journalArticlepeer-review

Abstract

A 2-1 multistage noise-shaping (MASH) switched-capacitor (SC) delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. We developed two separate segmented integration techniques to implement the first two integrators in the DSM. The techniques use both an inverter (IVT)-based opamp and a source-coupled-pair (SCP)-based opamp to relay the charge integration operation. This increases performance while saving power. The first integrator also operates more slowly during output sampling to further reduce power consumption. Operating at a 5-MS/s sampling rate, this chip consumes 175 μW from a 1-V supply. For a 25-kHz signal bandwidth, it achieves a 96.1-dB signal-to-noise ratio (SNR), a 94.6-dB signal-to-noise-plus-distortion ratio (SNDR) and a 98.5-dB dynamic range (DR). Its active area is 1.13 × 0.34mm2.

Original languageEnglish
Article number8765753
Pages (from-to)2523-2531
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume54
Issue number9
DOIs
StatePublished - Sep 2019

Keywords

  • Analog-digital conversion
  • delta-sigma modulator (DSM)
  • multistage noise-shaping (MASH)
  • switched-capacitor (SC) circuit

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