A 1-V 175-μ W 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques

Sheng Hui Liao; Jieh-Tsorng Wu

doi:10.1109/JSSC.2019.2925273

A 1-V 175-μ W 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques

Research output: Contribution to journal › Article › peer-review

Abstract

A 2-1 multistage noise-shaping (MASH) switched-capacitor (SC) delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. We developed two separate segmented integration techniques to implement the first two integrators in the DSM. The techniques use both an inverter (IVT)-based opamp and a source-coupled-pair (SCP)-based opamp to relay the charge integration operation. This increases performance while saving power. The first integrator also operates more slowly during output sampling to further reduce power consumption. Operating at a 5-MS/s sampling rate, this chip consumes 175 μW from a 1-V supply. For a 25-kHz signal bandwidth, it achieves a 96.1-dB signal-to-noise ratio (SNR), a 94.6-dB signal-to-noise-plus-distortion ratio (SNDR) and a 98.5-dB dynamic range (DR). Its active area is 1.13 × 0.34mm².

Original language	English
Article number	8765753
Pages (from-to)	2523-2531
Number of pages	9
Journal	IEEE Journal of Solid-State Circuits
Volume	54
Issue number	9
DOIs	https://doi.org/10.1109/JSSC.2019.2925273
State	Published - Sep 2019

Keywords

Analog-digital conversion
delta-sigma modulator (DSM)
multistage noise-shaping (MASH)
switched-capacitor (SC) circuit

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title = "A 1-V 175-μ W 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques",

abstract = "A 2-1 multistage noise-shaping (MASH) switched-capacitor (SC) delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. We developed two separate segmented integration techniques to implement the first two integrators in the DSM. The techniques use both an inverter (IVT)-based opamp and a source-coupled-pair (SCP)-based opamp to relay the charge integration operation. This increases performance while saving power. The first integrator also operates more slowly during output sampling to further reduce power consumption. Operating at a 5-MS/s sampling rate, this chip consumes 175 μW from a 1-V supply. For a 25-kHz signal bandwidth, it achieves a 96.1-dB signal-to-noise ratio (SNR), a 94.6-dB signal-to-noise-plus-distortion ratio (SNDR) and a 98.5-dB dynamic range (DR). Its active area is 1.13 × 0.34mm2.",

keywords = "Analog-digital conversion, delta-sigma modulator (DSM), multistage noise-shaping (MASH), switched-capacitor (SC) circuit",

author = "Liao, {Sheng Hui} and Jieh-Tsorng Wu",

year = "2019",

month = sep,

doi = "10.1109/JSSC.2019.2925273",

language = "English",

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T1 - A 1-V 175-μ W 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques

AU - Liao, Sheng Hui

AU - Wu, Jieh-Tsorng

PY - 2019/9

Y1 - 2019/9

N2 - A 2-1 multistage noise-shaping (MASH) switched-capacitor (SC) delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. We developed two separate segmented integration techniques to implement the first two integrators in the DSM. The techniques use both an inverter (IVT)-based opamp and a source-coupled-pair (SCP)-based opamp to relay the charge integration operation. This increases performance while saving power. The first integrator also operates more slowly during output sampling to further reduce power consumption. Operating at a 5-MS/s sampling rate, this chip consumes 175 μW from a 1-V supply. For a 25-kHz signal bandwidth, it achieves a 96.1-dB signal-to-noise ratio (SNR), a 94.6-dB signal-to-noise-plus-distortion ratio (SNDR) and a 98.5-dB dynamic range (DR). Its active area is 1.13 × 0.34mm2.

AB - A 2-1 multistage noise-shaping (MASH) switched-capacitor (SC) delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. We developed two separate segmented integration techniques to implement the first two integrators in the DSM. The techniques use both an inverter (IVT)-based opamp and a source-coupled-pair (SCP)-based opamp to relay the charge integration operation. This increases performance while saving power. The first integrator also operates more slowly during output sampling to further reduce power consumption. Operating at a 5-MS/s sampling rate, this chip consumes 175 μW from a 1-V supply. For a 25-kHz signal bandwidth, it achieves a 96.1-dB signal-to-noise ratio (SNR), a 94.6-dB signal-to-noise-plus-distortion ratio (SNDR) and a 98.5-dB dynamic range (DR). Its active area is 1.13 × 0.34mm2.

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KW - delta-sigma modulator (DSM)

KW - multistage noise-shaping (MASH)

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