A 1-V 1.25-GS/S 8-bit self-calibrated flash ADC in 90-nm digital CMOS

Hairong Yu; Mau-Chung Chang

doi:10.1109/TCSII.2008.921596

A 1-V 1.25-GS/S 8-bit self-calibrated flash ADC in 90-nm digital CMOS

Hairong Yu^*, Mau-Chung Chang

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Contribution to journal › Article › peer-review

47 Scopus citations

Abstract

We present an 8-bit 1.25-GS/s flash analog-to-digital converter (ADC) in 90-nm digital CMOS with wide analog input bandwidth and low power dissipation. The ADC employs two key techniques: a self-biased track-and-hold amplifier which enhances the ADC full-scale voltage and enables the converter operating under a single 1-V supply; and an improved calibration scheme based on reference pre-distortion to enhance the ADC linearity without sacrificing its sampling speed. The prototype converter thus achieves 7-, 6.9-, 6.5-bit ENOB at 1.25 GS/s for input signal frequencies of 10 MHz, 600 MHz, and 1.3 GHz, respectively, and better than 52-dB SFDR across the full Nyquist-band, while dissipating 207 mW from a single 1-V supply.

Original language	English
Pages (from-to)	668-672
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	55
Issue number	7
DOIs	https://doi.org/10.1109/TCSII.2008.921596
State	Published - 1 Jul 2008

Keywords

Calibration
Flash analog-to-digital converter (ADC)
Offset correction
Ssource follower
Unity-gain buffer

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@article{e38f27def84841b58a384eebd3211392,

title = "A 1-V 1.25-GS/S 8-bit self-calibrated flash ADC in 90-nm digital CMOS",

abstract = "We present an 8-bit 1.25-GS/s flash analog-to-digital converter (ADC) in 90-nm digital CMOS with wide analog input bandwidth and low power dissipation. The ADC employs two key techniques: a self-biased track-and-hold amplifier which enhances the ADC full-scale voltage and enables the converter operating under a single 1-V supply; and an improved calibration scheme based on reference pre-distortion to enhance the ADC linearity without sacrificing its sampling speed. The prototype converter thus achieves 7-, 6.9-, 6.5-bit ENOB at 1.25 GS/s for input signal frequencies of 10 MHz, 600 MHz, and 1.3 GHz, respectively, and better than 52-dB SFDR across the full Nyquist-band, while dissipating 207 mW from a single 1-V supply.",

keywords = "Calibration, Flash analog-to-digital converter (ADC), Offset correction, Ssource follower, Unity-gain buffer",

author = "Hairong Yu and Mau-Chung Chang",

year = "2008",

month = jul,

day = "1",

doi = "10.1109/TCSII.2008.921596",

language = "English",

volume = "55",

pages = "668--672",

journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",

issn = "1549-8328",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "7",

}

TY - JOUR

T1 - A 1-V 1.25-GS/S 8-bit self-calibrated flash ADC in 90-nm digital CMOS

AU - Yu, Hairong

AU - Chang, Mau-Chung

PY - 2008/7/1

Y1 - 2008/7/1

N2 - We present an 8-bit 1.25-GS/s flash analog-to-digital converter (ADC) in 90-nm digital CMOS with wide analog input bandwidth and low power dissipation. The ADC employs two key techniques: a self-biased track-and-hold amplifier which enhances the ADC full-scale voltage and enables the converter operating under a single 1-V supply; and an improved calibration scheme based on reference pre-distortion to enhance the ADC linearity without sacrificing its sampling speed. The prototype converter thus achieves 7-, 6.9-, 6.5-bit ENOB at 1.25 GS/s for input signal frequencies of 10 MHz, 600 MHz, and 1.3 GHz, respectively, and better than 52-dB SFDR across the full Nyquist-band, while dissipating 207 mW from a single 1-V supply.

AB - We present an 8-bit 1.25-GS/s flash analog-to-digital converter (ADC) in 90-nm digital CMOS with wide analog input bandwidth and low power dissipation. The ADC employs two key techniques: a self-biased track-and-hold amplifier which enhances the ADC full-scale voltage and enables the converter operating under a single 1-V supply; and an improved calibration scheme based on reference pre-distortion to enhance the ADC linearity without sacrificing its sampling speed. The prototype converter thus achieves 7-, 6.9-, 6.5-bit ENOB at 1.25 GS/s for input signal frequencies of 10 MHz, 600 MHz, and 1.3 GHz, respectively, and better than 52-dB SFDR across the full Nyquist-band, while dissipating 207 mW from a single 1-V supply.

KW - Calibration

KW - Flash analog-to-digital converter (ADC)

KW - Offset correction

KW - Ssource follower

KW - Unity-gain buffer

UR - http://www.scopus.com/inward/record.url?scp=48849096425&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2008.921596

DO - 10.1109/TCSII.2008.921596

M3 - Article

AN - SCOPUS:48849096425

VL - 55

SP - 668

EP - 672

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

SN - 1549-8328

IS - 7

ER -

A 1-V 1.25-GS/S 8-bit self-calibrated flash ADC in 90-nm digital CMOS

Abstract

Keywords

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