Abstract
We present an 8-bit 1.25-GS/s flash analog-to-digital converter (ADC) in 90-nm digital CMOS with wide analog input bandwidth and low power dissipation. The ADC employs two key techniques: a self-biased track-and-hold amplifier which enhances the ADC full-scale voltage and enables the converter operating under a single 1-V supply; and an improved calibration scheme based on reference pre-distortion to enhance the ADC linearity without sacrificing its sampling speed. The prototype converter thus achieves 7-, 6.9-, 6.5-bit ENOB at 1.25 GS/s for input signal frequencies of 10 MHz, 600 MHz, and 1.3 GHz, respectively, and better than 52-dB SFDR across the full Nyquist-band, while dissipating 207 mW from a single 1-V supply.
Original language | English |
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Pages (from-to) | 668-672 |
Number of pages | 5 |
Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
Volume | 55 |
Issue number | 7 |
DOIs | |
State | Published - 1 Jul 2008 |
Keywords
- Calibration
- Flash analog-to-digital converter (ADC)
- Offset correction
- Ssource follower
- Unity-gain buffer