A 1-GS/s FFT/IFFT Processor for UWB Applications

Yu Wei Lin*, Hsuan Yu Liu, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

181 Scopus citations

Abstract

In this paper, we present a novel 128-point FFT/IFFT processor for ultrawideband (UWB) systems. The proposed pipelined FFT architecture, called mixed-radix multipath delay feedback (MRMDF), can provide a higher throughput rate by using the multidata-path scheme. Furthermore, the hardware costs of memory and complex multipliers in MRMDF are only 38.9% and 44.8% of those in the known FFT processor by means of the delay feedback and the data scheduling approaches. The high-radix FFT algorithm is also realized in our processor to reduce the number of complex multiplications. A test chip for the UWB system has been designed and fabricated using 0.18-μm single-poly and six-metal CMOS process with a core area of 1.76 × 1.76 mm2, including an FFT/IFFT processor and a test module. The throughput rate of this fabricated FFT processor is up to 1 Gsample/s while it consumes 175 mW. Power dissipation is 77.6 mW when its throughput rate meets UWB standard in which the FFT throughput rate is 409.6 Msample/s.

Original languageEnglish
Pages (from-to)1726-1734
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume40
Issue number8
DOIs
StatePublished - 1 Aug 2005

Keywords

  • Fast Fourier transform (FFT)
  • Orthogonal frequency division multiplexing (OFDM)
  • Ultrawideband (UWB)

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