A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging

Xicheng Jiang*, Mau-Chung Chang

*Corresponding author for this work

Research output: Contribution to journalArticle

70 Scopus citations

Abstract

A 2-GS/s 6-bit ADC with time-interleaving is demonstrated in 0.18-μm one-poly six-metal CMOS. A triple-cross connection method is devised to improve the offset averaging efficiency. Circuit techniques, enabling a state-of-the-art figure-of-merit of 3.5 pJ per conversion step, are discussed. The peak DNL and INL are measured as 0.32 LSB and 0.5 LSB, respectively. The SNDR and SFDR have achieved 36 and 48 dB, respectively, with 4 MHz input signal. Near Nyquist input frequencies, the SNDR and SFDR maintain above 30 and 35.5 dB, respectively, up to 941 MHz. The complete ADC, including front-end track-and-hold amplifiers and clock buffers, consumes 310 mW from a 1.8-V supply while operating at 2-GHz conversion rate. The prototype ADC occupies an active chip area of 0.5 mm 2.

Original languageEnglish
Pages (from-to)532-535
Number of pages4
JournalIEEE Journal of Solid-State Circuits
Volume40
Issue number2
DOIs
StatePublished - 1 Feb 2005

Keywords

  • Analog-to-digital converter (ADC)
  • Averaging
  • CMOS
  • Interleaving
  • Track/hold
  • Triple-cross connection

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